The present invention is generally directed to the testing of large complex logic circuits by scan test methodologies wherein test patterns or vectors are shifted into shift register latches which are components of functional registers in the logic circuit. Said patterns are usually generated by random test vector generators but my invention is not limited to such means of test pattern generation. More particularly, the present invention is directed to the testing of said large complex circuits to detect AC or delay faults by shifting into a particular shift register latch a pattern of a logic "0" followed by a logic "1" or vice versa in such a manner as to cause a transition of the observable output of a logic circuit under test. Even more particularly the invention is directed to a method of determining the optimal connection of the stages of the shift register to achieve the highest test coverage possible without the addition of extra shift-register latches which have no function other than to improve the test coverage.
Digital integrated circuits are conventionally tested by successively applying test vectors to the inputs of the circuits. Unless means are provided to apply these test vectors using logic already in the circuit, all the inputs to the logic circuit must be connected to primary inputs and all the outputs must be observable through primary outputs. Scan test methodologies, such as Level Sensitive Scan Design (LSSD), use the flip-flops in registers within the logic chip to present the test vectors to the combinational logic tinder test. Means must be provided to allow the flip-flops to shift data in and out when in so called scan mode, usually by daisy-chaining the flip-flops into a shift register latch scan chain. Means may be provided on chip to generate the test vectors and to compact the results of the test for comparison with the correct results to be expected from a good circuit.
It is well know to those skilled in the art that this scan technique may be extended to the testing for AC delay faults. i.e. those circuit faults wherein the circuits behave correctly according to the static logical equations expected but do not assume these values in the correct lime but take longer then expected to assume the correct value. Using scan techniques to detect AC delay faults requires a time sequence of first and second test vectors. Said first test vector sensitizes the logic path to be tested. Said second test vector provides the appropriate plurality of logical "0" to "1" and "1" to "0" transitions from the first test vector to cause an observable logical output to switch. This is captured into a shift-register latch with an appropriate clock. If the correct value is captured, it is seen that the sensitized path switched with no more delay time then the time between the presentation of the second test vector and the capture clock.
The goal of such test means is to achieve the maximum fault coverage possible at a given acceptable cost. The three elements of cost are test vector design, test run time on tile hardware under test, and additional hardware which must be added to a functional design to implement the test means. There is always an engineering compromise in selecting values for each of these cost elements, however since the additional hardware which must be added to the functional design is present in each manufactured circuit it is the highest cost item in general.
U.S. Pat. No. 5,278,842 issued Jan. 11,1994 to R. W. Berry Jr. and J.Savir and assigned to the International Business Machines Corporation, attempts to maximize fault coverage with the addition of additional test only latches. They teach the method of selectively associating latch outputs in a level sensitive scan design latch string with logic circuit inputs such that latch outputs from latches which are adjacent on the scan chain do not feed the same cone of logic. The method taught therein maximizes the delay fault coverage by adding dummy latch elements when necessary between adjacent latches in the string. Said dummy latch elements are for test purposes only and do not feed any logic circuit input signal lines. As mentioned above, for cost reasons it is a priori undesirable to add such test only hardware. My invention teaches how to maximize the delay fault test coverage without the addition of such dummy latches. In addition, we would note that there are patents of which we are aware which are listed below with a brief discussion of each of the patents.
U.S. Pat. No. 5,023,875, issued Jun. 11, 1991 to G. W. Lee and G. D. Underwood and assigned to Hughes Aircraft Company, shows a system for detecting scan faults, including delay faults, by connecting first and second serial data shift register stages to a logic circuit under test such that said first and second stages are always separated by a third serial data shift register stage. Said third serial data shift register stage is always a dummy stage in the meaning of the prior cited U.S. Pat. No. 5,278,842, i.e. it does not have any connection between its output and any input of the logic circuit under test. This system therefore has a high ratio of added test only latches to functional latches and is an inefficient means of increasing the delay fault coverage. However, it guarantees that all paths can be sensitized.
U.S. Pat. No. 5,187,712, issued Feb. 16, 1993 to J. A. Malleo-Roach et al. and assigned to AT&T Bell Laboratories teaches a method of partitioning a logic circuit containing groups of combinational elements fed by registers into sub-cones of logic of predetermined input width by the addition of a plurality of test point multiplexors. Said subcones of logic are then pseudo-exhaustively tested with a set of test vectors generated with a test vector generator. With this method it is usually impossible to assign separate vectors of tile set of test vectors to each input of each subcone so that no subcone has two or more of its inputs supplied with the same vector. This prevents the test patterns from sensitizing all AC delay paths. However, this patent is not concerned with AC delay fault detection but only static combinational faults. The coverage lost by the overlapping of the subcone inputs is gained back by the generation of an additional set of vectors made of a linear combinations of the previously generated test vectors. This technique does not yield increased AC delay coverage.
Prior art: Publications
B. I. Dervisoglu and G. E. Strong "Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement" in Proceedings of 1991 IEEE International Test Conference, P365 et seq., teach a method of implementing the scheme of U.S. Pat. No. 5,023,875 cited above using a so-called double strobe flip flop. This scheme is actually two parallel scan chains, independently loaded such that each input of each logic cone is fed from stage n of the first of said two chains and the input of tile flip flop of stage n of the said first chain is fed from stage n of said second scan chain. This guarantees that the test vector sequence necessary to sensitize all potential delay fault paths can be generated. The amount of hardware in the scan chain is doubled and the wiring to connect the scan chains is also doubled. This is a large cost to get the necessary test coverage.